1. Field of the Invention
The invention relates generally to semiconductor fabrication, and more particularly to back end of line (BEOL) techniques that reduce manufacturing errors related to via metal melt extrusion
2. Background of the Invention
Semiconductor wafers are manufactured in accordance with a process flow. The process flow comprises all of the different processing steps, such as etching and photolithography, involved in the process of manufacturing semiconductor wafers. A typical process flow can consist of 300-400 steps, wherein each of these steps contributes to the final circuit structures formed within a single chip on the semiconductor wafer. A typical process flow is divided into two main sub-processes. The first of these main sub-processes can be termed the front end of line (FEOL) process, and the second of these main sub-processes can be termed the back end of line (BEOL) process.
The FEOL process typically starts from the laser marking of wafer lots and continues through the formation of Shallow Trench Isolation (STI), implantation of P and N wells, etching of poly, and followed by implantation of various regions such as the drain and source regions of a transistor structure.
The BEOL process can comprise the formation of metal lines and via contacts between metal lines in different layers of the wafer. Often, there are two, or more metal layers comprising metal interconnection lines. Vias run between two metal layers. The BEOL process is a process whereby devices in the FEOL layers are interconnected with other circuits forming the chip and to the outside world.
Metal layers are typically formed via a Physical Vapor Deposition (PVD) process. A typical PVD process comprises the deposition of metal layers as followed. These metal layers typically comprise Ti, TiN, Al or AlCu, and Ti and TiN. First, for example, Ti layer and TiN layer are deposited followed by the deposition of an Al layer, and then the deposition of Ti layer and TiN layer.
Vias are then patterned in the lower metal layers and further metal layers are formed over the lower metal layers. Conventionally, a via is formed by first forming metal adhesion layers within the patterned via hole and then forming a tungsten (W) plug inside of the metal adhesion layers. The metal adhesion layers often comprise a Titanium (Ti) metal layer formed within the patterned via hole and a Titanium Nitride (TiN) layer formed with the Ti Layer. The Ti Layer is often formed in a first deposition chamber (CH 1) and the TiN layer is often formed in a second deposition chamber (CH 2). The Ti adhesion layer can be formed using PVD, or more specifically Ionized Metal Plasma (IMP) PVD. The TiN adhesion layer can be formed using Metal Organic Chemical Vapor Deposition (MOCVD)
It will be understood that the metal adhesion layer formation can subject the wafer to high heat. For example, in a conventional process, the temperature in CH 1 can be as high as 200° C. and rising throughout the process. The temperature in CH 2 can be as high as 450° C. Unfortunately, the Al in the metal layers can melt at temperatures around 600° C. The back-to-back heating processes can actually cause the wafer temperature to exceed the Al melting point, which cause the Al to extrude into the via. This can increase the via resistance and lead to device performance problems and even failures.
One solution to this problem is to reduce the heat cycle times associated with deposition of the Ti layers by thinning the Ti layers in adhesion layer; however, such solutions are not ideal since reducing the heat cycling time by reducing the thickness of the Ti layers will reduce reliability as well.